Informatics Publishing Limited

R. Vijay Sai ¹, S. Saravanan ¹, V. Anandkumar ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Abstract

This article shows the importance of security in memory for VLSI circuits based on data scrambling and overcome attacks. Security information stored in memory is very valuable. The model should not be prone to intruder attacks. The proposed method provides scrambling of information by data scrambling vectors. Instead of using some extra table for scrambling the data in cache memories, the data is divided into two halves and scrambled within to overcome extra hardware and memory requirement. This method is implemented in Verilog HDL using Model Sim which has improvement in area and memory requirement. This method is more suitable for value added applications such as smart cards and bio metric applications.

Keywords

Cache Read and Write Operations, Scrambling Vectors, Security in Memory

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V. Anandkumar ¹, E. Venkatesan ¹, Baldev Raj ¹, C. Karthikeyan ², R. S. Babu ²

Affiliations
1 Indira Gandhi Centre for Atomic Research, Kalpakkam, IN
2 The Welding Research Institute, BHEL, Tiruchirapalli, IN

Abstract

Steam generators are critical components for the Prototype fast Breeder Reactor being designed at the Indira Gandhi Centre for Atomic Research, Kalpakkam. A leak in the steam generators can have serious consequences leading to rupture of steam generator tubes. Consequently, by introducing a known leak in the experimental loop, data is required to be generated which can predict the response of the material to the leak as a function of leak rate, time, temperature, steam pressure and the size of the microhole as a result of sodium water reaction.

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